TLP:CLEAR
RESOLVED · HISTORICAL
// Vulnerability Advisory — CPU Side-Channel / Information Disclosure (Speculative Execution) · Intel · AMD · ARM · IBM

SPECTRE / MELTDOWN

COMPILED: 2026-09-13  |  PREVIOUSLY COMPILED: 2026-08-30  |  CVE: CVE-2017-5753 · CVE-2017-5715 · CVE-2017-5754 (original three; see Section 09 for the wider family)  |  CWE: CWE-1303 (modern classification) · CWE-200 / CWE-203 (original per-CVE assignment)  |  SOURCES: 17
CVSS: 5.6 (MEDIUM, per NVD — see analytical note)
Affected: Virtually all Intel x86 CPUs since 1995; many AMD and ARM cores; IBM Power
Disclosed: 2018-01-03 (embargo broken early; coordinated date was 2018-01-09)
Patch Date: 2018-01-03 onward (OS/microcode/compiler — no single patch)
KEV Added: Not listed — see Section 06
EPSS: 0.74 – 0.94 across the three CVEs
5.6
CVSS v3 Base Score (NVD, all three CVEs)
CVE-2017-5754 (Meltdown)
+ CVE-2017-5753 (Spectre v1) · CVE-2017-5715 (Spectre v2) — all scored identically by NVD
CVSS:3.0/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:N/A:N
20+
Named transient-execution attack variants disclosed since 2018 (Foreshadow, MDS, Retbleed, Downfall, and more)
8 YRS
And counting — years this weakness class has continued producing new CVEs
0
Confirmed real-world breaches publicly attributed to Spectre/Meltdown-class exploitation, as of this compile
≤30%
Peak throughput loss on I/O-heavy workloads from early 2018 KPTI mitigations
01
Situation Overview

Meltdown and Spectre are the founding members of an entire vulnerability class — transient execution attacks — disclosed on January 3, 2018 (early, and simultaneously) after roughly seven months of coordinated, multi-vendor secrecy. Unlike a software bug confined to one library or one product, these are hardware design flaws in the speculative-execution and branch-prediction logic that virtually every modern high-performance CPU relies on for speed. Meltdown (CVE-2017-5754) let an unprivileged process read arbitrary kernel memory on affected Intel (and some ARM) processors; Spectre (CVE-2017-5753, Variant 1, "Bounds Check Bypass," and CVE-2017-5715, Variant 2, "Branch Target Injection") let an attacker trick almost any modern CPU's branch predictor into speculatively executing code paths that leak data across security boundaries — including, critically, from inside a web browser's JavaScript sandbox.

The scale of exposure was without precedent for a CPU-level bug: virtually every Intel x86 processor shipped since 1995, many ARM Cortex-A cores used in smartphones and embedded devices, and IBM Power processors were affected — meaning nearly every laptop, desktop, server, smartphone, and cloud instance running any mainstream operating system in early 2018 required some combination of OS, microcode, and compiler-level mitigation. Because cloud computing depends on strong isolation between co-tenant virtual machines sharing physical CPUs, Spectre and Meltdown were treated as an existential threat to the multi-tenant cloud model specifically — a VM on a shared host could, in principle, read data belonging to a different customer's VM on the same physical processor.

Spectre/Meltdown matter to a CTI practice in 2026 not because of documented breaches — there remains no confirmed public case of criminal or espionage exploitation, discussed candidly in Section 06 — but because they permanently changed the threat model for hardware. They created an entire, still-active academic and red-team research subfield (transient execution / microarchitectural side-channel attacks) that has produced upward of twenty additional named variants since 2018 (Foreshadow, the MDS family, SWAPGS, Retbleed, Downfall, Zenbleed, Inception, and others), several as recently as 2023–2024. Any organization operating shared/multi-tenant compute, high-assurance isolation boundaries (hypervisors, SGX-style enclaves, browser sandboxes), or long-lifecycle hardware should treat this as a permanent category of residual risk rather than a closed 2018 incident.

Who is at risk today: primarily cloud providers and any organization relying on hardware-enforced isolation between mutually distrusting workloads on shared silicon. For general enterprise endpoints and servers, the original three CVEs have been mitigated for years through routine OS, browser, and firmware updates; the residual risk sits almost entirely with unpatched legacy/embedded systems and with the ongoing discovery of new variants against which today's mitigations were not designed.

02
Root Cause Analysis CWE Classification + Architectural Failure
CWE-1303 Non-Transparent Sharing of Microarchitectural Resources
Hardware structures shared across execution contexts — caches, branch predictors, execution ports, internal buffers — can violate the architectural isolation an operating system or hypervisor believes it is enforcing, if the extent of that sharing is not accounted for in the security model (MITRE CWE-1303). This weakness class was defined by MITRE specifically in response to Spectre/Meltdown-style attacks; the original 2018 CVE records predate CWE-1303 and were filed under the more generic CWE-200 (Exposure of Sensitive Information) and CWE-203 (Observable Discrepancy) instead.

Modern CPUs execute far ahead of the program's true control flow to hide memory latency: they guess which way a branch will go (branch prediction) and begin executing instructions along the guessed path before the guess is confirmed (speculative execution), and they let independent instructions run out of program order when their inputs are ready (out-of-order execution). If the guess is wrong, the CPU architecturally discards the speculative results — but it does not undo their microarchitectural side effects, chiefly what got pulled into the CPU cache during the speculative window. Spectre and Meltdown both exploit this gap between "architecturally invisible" and "microarchitecturally observable."

Spectre (CVE-2017-5753 / CVE-2017-5715) works by mistraining a CPU's branch predictor: an attacker repeatedly executes a branch with in-bounds, harmless inputs until the predictor learns to expect that branch to be taken, then supplies an out-of-bounds or attacker-chosen input on the next call. The CPU speculatively executes the mispredicted path — briefly touching memory the program was never supposed to access — before rolling back the architectural state. The touched memory's address leaves a measurable trace in cache timing, which the attacker recovers with a cache side-channel (classically, Flush+Reload).

Meltdown (CVE-2017-5754) is narrower but more severe on affected Intel processors: it exploits the fact that some out-of-order cores perform a memory access speculatively before checking whether the requesting process is actually permitted to read that address. By the time the permission-check exception fires and the CPU discards the result, the accessed kernel-memory byte has already been used to influence a subsequent, attacker-controlled memory access — again leaving a cache-timing trace an unprivileged user-mode process can read out, effectively bypassing the hardware-enforced user/kernel memory boundary entirely.

Both are hardware design flaws, not implementation bugs in a specific piece of software — which is why there is no single authoritative "patch" the way there is for Heartbleed. Every mitigation (Section 05, Section 08) works around the underlying microarchitecture rather than fixing it, and true architectural fixes only arrived in later CPU generations that redesigned the affected prediction/execution logic.

03
Vulnerability Lifecycle
01
Discovery
2017-06
02
Disclosure
2018-01-03
03
Patch Chaos
2018-01 → 02
04
Variant Cascade
2018 → present
05
Resolution
Partial / ongoing

Google Project Zero researcher Jann Horn discovered the underlying speculative-execution issue independently around June 2017; academic teams at Graz University of Technology (Meltdown) and a separate multi-institution group led by Paul Kocher (Spectre) arrived at closely related findings around the same period. Intel, AMD, ARM, and the major cloud and OS vendors were brought into a coordinated disclosure process under strict embargo beginning mid-2017, with a planned joint public disclosure date of January 9, 2018.

The embargo broke six days early. Observers—including this repository's own review of contemporaneous reporting—traced the leak to public Linux kernel mailing-list activity: patches implementing Kernel Page Table Isolation (KPTI, initially called KAISER) began appearing in the open Linux kernel tree in November–December 2017 without public explanation, drawing pointed speculation from security researchers about what critical, hardware-level issue could require such an invasive and performance-costly fix. The Register published a story on January 2, 2018 naming the likely CPU flaw; Google and the Graz team published full technical details and named the vulnerabilities the next day, January 3, forcing every vendor in the coordination group to accelerate their own advisories and patches simultaneously and without their planned lead time.

What followed was an unusually public vendor-response failure. Initial OS-level (KPTI) and firmware-level (microcode) mitigations shipped within days, but by January 22, 2018, Intel was forced to advise OEMs, cloud providers, and end users to stop deploying its own Spectre microcode updates after widespread reports of spontaneous reboots on Broadwell, Haswell, Sandy Bridge, Ivy Bridge, Skylake, and Kaby Lake systems — a rare case of a vendor publicly retracting its own emergency security patch due to stability regressions, in the middle of the highest-profile CPU vulnerability disclosure in the industry's history. Revised, stable microcode did not fully roll out across the affected product lines for several more months. Since then, the "lifecycle" has never fully closed: the same underlying speculative-execution/branch-prediction weakness (CWE-1303) has continued to yield new named variants and CVEs from 2018 through at least 2024 (Section 07), making Spectre/Meltdown better understood as the opening chapter of an ongoing research area than as a single closed incident.

04
Disclosure Analysis
Disclosure TypeCoordinated multi-vendor — embargo broken early by external speculation
Discovered ByJann Horn (Google Project Zero); Graz UT team; Paul Kocher et al.
Reported To Vendor~2017-06 (Google to Intel); coordination group formed by mid-2017
PoC ReleasedConcurrent with disclosure — academic PoCs, no pre-patch weaponized exploit observed
PoC vs PatchMitigations available at disclosure, though incomplete and later partially retracted
Vendor ResponseFast but unstable — Intel told customers to stop installing its own patch within 3 weeks
Community ReactionAlarm plus scrutiny of vendor conduct — CEO stock-sale controversy, 32+ lawsuits
CVD Policy FollowedLargely — but the coordination window was cut short by external leaks, not by the participants

Beyond the technical embargo break, the Spectre/Meltdown disclosure is inseparable from a serious corporate-governance controversy. Intel CEO Brian Krzanich sold approximately $24 million of Intel stock — reducing his holdings to the minimum required under his compensation plan — in late November 2017, months after Intel had been notified of the flaws (around June 2017) and shortly after adopting a 10b5-1 trading plan on October 30, 2017. Because the trading plan was adopted after Intel already knew about the vulnerabilities, U.S. senators publicly called on the SEC and Department of Justice to investigate the timing, and Intel faced its first shareholder lawsuit over the matter within days of public disclosure; the company was ultimately named in more than thirty class-action lawsuits related to Meltdown and Spectre, including securities claims alleging Intel made misleading statements about product security. This repository's confidence in the timeline of Intel's internal knowledge versus the stock sale is high (corroborated by Intel's own SEC filings and multiple independent outlets); confidence in whether the timing constituted actionable insider trading is low — that question was for regulators and courts to determine, and this card does not take a position on it.

The technical disclosure itself is a strong example of coordinated vulnerability disclosure under real-world pressure: the participating vendors maintained silence for roughly seven months, a genuinely difficult feat across dozens of organizations, and the eventual six-day-early release was a reaction to outside speculation rather than a breakdown among the coordinating parties. The subsequent patch-quality failure (Intel's own mitigation causing reboots) is the more instructive disclosure-adjacent lesson: an emergency, under-tested hardware-adjacent fix rushed out under public pressure introduced a second, self-inflicted reliability crisis on top of the original security one.

05
Technical Deep Dive Exploitation Mechanics · CVSS Breakdown · Affected Versions

A practical Spectre (Variant 1) attack against, for example, a web browser's JavaScript engine trains a bounds-check branch with in-range array indices in a tight loop, then supplies an out-of-range index. The CPU speculatively executes the array read using the attacker-chosen out-of-range index before the bounds check resolves, loading an out-of-bounds byte into a cache line whose address depends on the leaked byte's value. The attacker then times reads across a large probe array (Flush+Reload) to determine which cache line was populated, recovering the secret byte one bit-pattern at a time — entirely through the browser's JavaScript sandbox, with no native code execution required, which is what made Spectre relevant to literally every internet user's web browser rather than only to specialized local-access scenarios.

Meltdown's exploitation path against affected Intel CPUs is more direct: an unprivileged process attempts to read a kernel-memory address it has no permission to access. The out-of-order core begins the read and uses the (privileged, and therefore normally inaccessible) result to index into an attacker-allocated probe array — entirely inside the speculative execution window — before the delayed permission-check exception aborts the instruction. The now-cached probe-array entry, again recovered via cache-timing analysis, reveals the byte of kernel memory the process should never have been able to read, at rates fast enough (originally reported around 120KB/s, later PoCs went faster) to dump substantial kernel memory in minutes.

CVSS v3 Vector Breakdown — CVSS:3.0/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:N/A:N (as scored by NVD for all three original CVEs)
Attack Vector
LOCAL
NVD scores this as requiring local code execution — but in practice, "local" is trivially satisfied by a cloud VM tenant, or by JavaScript in a browser tab, understating real-world reach.
Attack Complexity
HIGH
Requires precise cache-timing measurement and branch-predictor manipulation — nontrivial to engineer, though public tooling has since made this routine for researchers.
Privileges Required
LOW
Any unprivileged local process or sandboxed script can attempt exploitation — no elevated OS privileges needed.
User Interaction
NONE
No victim action beyond running the attacker's code/script is required once that code is running.
Scope
CHANGED
Impact crosses the security boundary the CPU is supposed to enforce (process/VM/kernel isolation) — the defining characteristic of this vulnerability class.
Confidentiality
HIGH
Can leak arbitrary process/kernel/co-tenant memory, including cryptographic keys and credentials held in memory.
Integrity
NONE
A read-only information-disclosure primitive — it does not itself modify data or system state.
Availability
NONE
No direct denial-of-service effect; the targeted system continues normal operation throughout exploitation.
Affected Platforms
VendorAffectedVariant(s)Primary MitigationStatus
IntelVirtually all x86 CPUs since 1995 (excl. pre-2013 Atom, Itanium)Spectre v1, v2, MeltdownKPTI + microcode (IBRS/IBPB) + retpolineMitigated — routine since 2018
AMDMost CPU families (not vulnerable to classic Meltdown, per AMD's original statement)Spectre v1, v2Retpoline + microcodeMitigated — routine since 2018
ARMCortex-A75 and other high-performance coresSpectre v1, v2Firmware/OS mitigations per ARM whitepaperMitigated — routine since 2018
IBMPower7+ processorsSpectre v1, v2Firmware + OS mitigationsMitigated — routine since 2018
06
Exploitation in the Wild Threat Actors · Campaigns · KEV Status
NOT LISTED IN CISA KEV Checked against the current KEV catalog as of 2026-08-30
None of CVE-2017-5753, CVE-2017-5715, or CVE-2017-5754 appear in the CISA Known Exploited Vulnerabilities catalog. This is a genuine and notable data point, not an oversight: eight years after disclosure, and despite an entire subsequent research field building on the same underlying weakness, there remains no public evidence meeting KEV's bar of confirmed, in-the-wild criminal or espionage exploitation. Dell's own January 26, 2018 advisory stated plainly that "no 'real-world' exploits of these vulnerabilities have been reported to date, though researchers have produced proof-of-concepts" — and this repository found no credible, corroborated report changing that assessment as of this compile.
Family Timeline — Original Disclosure Through the Ongoing Variant Cascade
2018-01-03
Meltdown & Spectre Disclosed
Academic PoCs published; no weaponized exploit code released alongside disclosure, unusual for a vulnerability of this profile.
2018-05-21
Spectre-NG — Variants 3a & 4
CVE-2018-3640 (Rogue System Register Read) and CVE-2018-3639 (Speculative Store Bypass) disclosed by Microsoft Security Response Center and Google Project Zero, extending the same underlying class to new mechanisms.
2018-08-14
Foreshadow / L1TF
CVE-2018-3615, CVE-2018-3620, CVE-2018-3646 — a Meltdown-type attack against Intel SGX enclaves and L1 cache, defeating hardware-isolated "secure enclave" protections specifically.
2019-05-14
MDS Family — ZombieLoad, RIDL, Fallout
CVE-2018-12130 and related Microarchitectural Data Sampling CVEs leak data from internal CPU buffers rather than the cache directly, requiring a new mitigation generation (microcode + buffer-clearing instructions).
2022 → 2024
Retbleed, Downfall, Zenbleed, Inception/SRSO
Successive discoveries showed that retpoline (Retbleed, 2022, AMD/Intel), AVX-512 gather instructions (Downfall, 2023, Intel), register-file handling (Zenbleed, 2023, AMD), and return-stack prediction (Inception/SRSO, 2023, AMD) each reopened variations of the same fundamental weakness against supposedly-hardened CPUs.
2024 → present
Active Research Area, No Confirmed Breach
GhostRace, SLAM, TikTag, Indirector, and other 2024-era findings continue the pattern: active, credible academic/red-team research with no publicly documented real-world criminal exploitation of the class to date.
2026-09-13
Vulnpedia.com Check — No Public PoC Catalogued (CVE-2017-5754)
No ExploitDB, Nuclei, or CISA KEV entry exists for the headline Meltdown CVE as of this check, consistent with the KEV-absence finding above. Notably high EPSS (84.2%, 100th percentile) reflects broad theoretical applicability across affected CPU families rather than confirmed real-world weaponization.

No card currently on file in this repository documents an actor or incident tied to Spectre/Meltdown-class exploitation, and — unlike Heartbleed or PrintNightmare — this repository is not aware of a credible candidate incident to flag for future creation, precisely because no confirmed real-world breach has been publicly attributed to this vulnerability class. This absence is itself the most important analytical fact in this section; see Section 08 for why that does not mean the risk is negligible for the specific population (cloud multi-tenancy, hardware enclaves) it actually threatens.

07
Architectural Lessons Why this class of vulnerability keeps recurring

Spectre and Meltdown are the clearest demonstration on record that a performance optimization can be a permanent, structural security liability rather than a bug to be patched away. Speculative execution and branch prediction exist because they deliver real, substantial performance gains that the entire high-performance computing industry has depended on for over two decades; removing them outright would sacrifice a significant fraction of a modern CPU's throughput. Every mitigation shipped since 2018 — KPTI, retpoline, microcode barriers, buffer-clearing instructions — is consequently a workaround that trades some of that performance back for security, not a fix that restores the original design's safety at no cost. This is architecturally different from PrintNightmare (a fixable software logic error) or Heartbleed (a fixable missing bounds check): here, the "bug" is an inherent property of how the hardware was designed to be fast, discovered only after that design had shipped in billions of units already in the field.

The eight-year, twenty-plus-variant cascade that followed the original disclosure is the strongest evidence available that this is a genuine, open-ended weakness class (CWE-1303) rather than a pair of one-off bugs. Foreshadow defeated Intel's own hardware-isolated SGX enclaves — the very feature marketed as a defense against this class of attack. Retbleed, four years later, defeated retpoline — the mitigation the industry had settled on as retpoline's namesake defense against Spectre v2. Downfall and Zenbleed found entirely new leakage paths through vector-instruction and register-renaming logic nobody had scrutinized in the original 2018 analysis. Each new variant follows the same pattern: researchers find a microarchitectural resource (a buffer, a predictor, a register file) that is shared across security contexts in a way the CPU's documentation never made explicit, exactly matching CWE-1303's definition. There is no reason to expect this pattern to stop; CPU vendors continue shipping new speculative and out-of-order optimizations, and each one is a candidate for the next variant.

The durable lesson for defenders is to treat hardware-enforced isolation boundaries — hypervisor tenant separation, secure enclaves, browser process sandboxes, TrustZone/SGX-style trusted execution environments — as probabilistic rather than absolute, particularly where genuinely mutually-distrusting parties share physical silicon. Cloud providers responded to this reality with additional software-level isolation layers (stronger VM scheduling isolation, disabling simultaneous multithreading on sensitive workloads, dedicated-host offerings) precisely because they concluded the CPU alone could not be fully trusted to enforce the boundary its marketing had promised. Organizations building new trust boundaries on top of shared hardware today should assume this pattern continues rather than assume 2018's mitigations were the last word.

08
Purple Team Detection · Hunting · Patch Guidance · Compensating Controls
A · Detection
B · Threat Hunting
C · Patch Guidance
D · Compensating Controls

Detecting active exploitation of a cache-timing side channel from host or network telemetry alone is a fundamentally different problem than detecting a network exploit or a malicious file: there is no packet, no payload, and no syscall that is unambiguously "a Spectre attack" versus legitimate high-performance code. Realistic detection focuses on compliance/exposure verification and anomalous performance-counter patterns rather than a signature match.

Mitigation-presence verification (host inventory query, illustrative)
GET /sys/devices/system/cpu/vulnerabilities/{meltdown,spectre_v1,spectre_v2} # Expect: "Mitigation: PTI" (Meltdown), "Mitigation: usercopy/swapgs barriers" (Spectre v1), # "Mitigation: Retpolines, IBPB, IBRS_FW" (Spectre v2) on Linux hosts. # Any host returning "Vulnerable" for a mainline CVE 6+ years post-patch is a hygiene finding, not a live-attack signal.
Anomalous cache-timing / performance-counter activity (research-grade, high false-positive rate)
SELECT host, process, AVG(llc_misses), AVG(branch_mispredicts) FROM perf_counter_telemetry WHERE process NOT IN (approved_hpc_workloads) GROUP BY host, process HAVING AVG(llc_misses) > baseline_p99 AND AVG(branch_mispredicts) > baseline_p99 # Flags processes with statistically abnormal cache/branch-predictor activity worth manual review; # NOT a reliable standalone detector — legitimate cryptographic and HPC code trips this routinely.

The most actionable "detection" available to most organizations is exposure verification, not attack detection: confirm every host, hypervisor, and browser reports the expected mitigation state for its CPU generation, and treat any host still reporting "Vulnerable" for a mainline CVE this many years post-disclosure as a hygiene failure requiring remediation, not as evidence of an ongoing attack.

Hypothesis 1 — Mitigations silently disabled for performance. Because KPTI, retpoline, and related mitigations carry a real, measurable performance cost, hunt for hosts where mitigations were deliberately disabled (via kernel boot parameters such as mitigations=off, or BIOS/UEFI options) to reclaim throughput, particularly on database, storage, or HPC-tuned systems where administrators are most incentivized to trade security for speed.

Hypothesis 2 — Unpatched legacy hypervisor/firmware exposing multi-tenant risk. For any organization running its own virtualization infrastructure (rather than a major public cloud), verify hypervisor and CPU microcode versions specifically for tenant-isolation-relevant mitigations (L1TF/Foreshadow flush-on-VM-entry, MDS buffer clearing) — these are easy to miss because they are not part of routine OS patching and require separate hypervisor and firmware updates.

Hypothesis 3 — SGX/enclave or TEE-dependent applications assuming absolute isolation. Identify any application whose security design assumes an Intel SGX enclave, ARM TrustZone, or similar hardware TEE provides an unconditional confidentiality boundary, and confirm the design has been reassessed against Foreshadow-class attacks — several early SGX-dependent architectures (e.g., certain confidential-computing and DRM schemes) were designed before this class of attack was known and may still carry unstated risk in their threat model.

Primary MitigationOS kernel update (KPTI) + compiler/binary retpoline + CPU microcode — all three, not one
Release Date2018-01-03 onward; microcode revisions continued through mid-2018
Regression RiskHigh historically — Intel's own Jan 2018 microcode caused spontaneous reboots and was withdrawn
Testing RequiredFor any legacy system just now being remediated: stage microcode/firmware updates before fleet-wide rollout, given the documented 2018 stability history
Public PoC (vulnpedia.com)None catalogued for CVE-2017-5754, checked 2026-09-13 — academic PoCs exist but no weaponized public exploit is listed
Vendor AdvisoriesIntel, AMD, ARM, IBM, and every major OS/hypervisor vendor issued independent advisories
Out-of-Band PatchYes — accelerated by 6 days due to the embargo break
Superseded ByNot fully — later variants (Foreshadow, MDS, Retbleed, etc.) each required their own, separate mitigation on top of the original three

For virtually all currently-supported hardware and operating systems in 2026, the original three CVEs are fully mitigated by default in any maintained OS and current microcode/firmware. The residual patch-guidance work that remains relevant is: (1) confirming any long-lived legacy system (embedded, industrial, unsupported OS) that has never received post-2018 updates actually has the mitigations applied, and (2) confirming the full, later variant lineage (Foreshadow, MDS, Retbleed, Downfall, Zenbleed, and current-year findings) has also been addressed via hypervisor and firmware updates specifically, since OS patching alone does not cover every layer these later variants touch.

01
For unpatchable legacy/embedded systems, avoid co-locating mutually distrusting workloads on the same physical CPU entirely — dedicated hardware is the most reliable compensating control where software mitigation is unavailable.
02
Disable simultaneous multithreading (SMT/Hyper-Threading) on hosts running highly sensitive or multi-tenant workloads where several MDS-class variants specifically leak data across sibling hyperthreads.
03
Keep browsers current as the single highest-leverage control for the general population of end-user devices — modern browser engines implement site isolation and array-bounds hardening specifically to blunt Spectre-style JavaScript exploitation, independent of OS/CPU patch status.
04
For cloud/hosting providers still running older hypervisor versions, verify VM-exit cache-flushing and buffer-clearing mitigations (for L1TF and MDS specifically) are enabled — these are frequently a separate hypervisor configuration flag, not bundled automatically with guest OS patches.
05
Do not disable mitigations for performance without an explicit, documented risk acceptance — the temptation to run with mitigations=off on performance-sensitive infrastructure reintroduces the entire vulnerability class for a measurable but generally modest throughput gain on modern hardware.
09
CVE / CVSS / KEV Reference Full metadata block — original three + representative family members

The Spectre/Meltdown family has produced well over two dozen distinct CVEs across Intel, AMD, and ARM since 2018. A complete per-CVE accounting of every named variant (Foreshadow's 3 CVEs, the MDS family's 6+ CVEs, and a dozen more since) is out of scope for this card; the table below covers the three foundational CVEs in full and lists representative follow-on variants for reference and further research.

CVE-2017-5754 (Meltdown)
CVSS v3 Score5.6 (Medium)
Vector StringCVSS:3.0/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:N/A:N
CWECWE-200 (original); CWE-1303 (modern)
EPSS Score0.826 (99.65th percentile)
KEV StatusNot listed
CVE-2017-5753 (Spectre v1)
CVSS v3 Score5.6 (Medium)
Vector StringCVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:N/A:N
CWECWE-203 (original); CWE-1303 (modern)
EPSS Score0.938 (99.84th percentile)
KEV StatusNot listed
CVE-2017-5715 (Spectre v2)
CVSS v3 Score5.6 (Medium)
Vector StringCVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:N/A:N
CWECWE-203 (original); CWE-1303 (modern)
EPSS Score0.740 (99.46th percentile)
KEV StatusNot listed
Representative Family Members
Spectre-NG v3a / v4CVE-2018-3640 / CVE-2018-3639
Foreshadow / L1TFCVE-2018-3615 / -3620 / -3646
MDS (ZombieLoad/RIDL)CVE-2018-12130 (+5 related)
Retbleed (2022)CVE-2022-29900 / -29901
Downfall (2023, Intel)CVE-2022-40982
Zenbleed (2023, AMD)CVE-2023-20593
Inception / SRSO (2023, AMD)CVE-2023-20569
NoteList is illustrative, not exhaustive — treat each as a separate research target if directly relevant to your fleet
10
Cross-References Linked actor and incident cards
Threat Actors Who Weaponized This Vulnerability
No companion actor cards on file, and none are expected — no threat actor is publicly documented as having weaponized Spectre/Meltdown-class attacks in an operational campaign as of 2026-08-30 (see Section 06).
Incidents Where This Was the Initial Vector
No companion incident cards on file, and none are known to be warranted — no publicly attributed breach incident has cited Spectre/Meltdown-class exploitation as an initial access vector as of 2026-08-30.
11
References URLs are NOT defanged — navigate directly
NVD / NIST
Accessed: 2026-08-30
NVD / NIST
Accessed: 2026-08-30
NVD / NIST
Accessed: 2026-08-30
FIRST.org
Accessed: 2026-08-30
Google Project Zero / Original Research
Accessed: 2026-08-30
Wikipedia (secondary, corroborating)
Accessed: 2026-08-30
DataCenterDynamics
Accessed: 2026-08-30
The Washington Post
Accessed: 2026-08-30
CISA (Variants 3a/4)
Accessed: 2026-08-30
Wikipedia — Foreshadow
Accessed: 2026-08-30
Wikipedia — Microarchitectural Data Sampling
Accessed: 2026-08-30
GitHub (speed47/spectre-meltdown-checker)
Accessed: 2026-08-30